The present disclosure relates to integrated circuit (IC) fabrication, and more specifically, to a gate cut isolation formed as a layer against a sidewall in a partially formed dummy gate material mandrel, an IC including the same and a method of forming the gate cut isolation.
Advanced manufacturing of ICs requires formation of individual circuit elements, e.g., field-effect-transistors (FETs) and the like, based on specific circuit designs. A FET generally includes source, drain, and gate regions. The gate region is placed between the source and drain regions and controls the current through a channel region (often shaped as a semiconductor fin) between the source and drain regions. Gates may be composed of various metals and often include a work function metal which is chosen to create desired characteristics of the FET. Transistors may be formed over a substrate and may be electrically isolated with an insulating dielectric layer, e.g., inter-level dielectric (ILD) layer. Contacts may be formed to each of the source, drain, and gate regions through the dielectric layer in order to provide electrical connection between the transistors and other circuit elements that may be formed subsequent to the transistor in other metal levels.
Fin-type field effect transistor (finFETs) are formed by creating a number of semiconductor fins on a substrate and placing a gate conductor perpendicularly across the fins. A finFET is created by the gate forming a channel region below the gate in the fin, and source/drain regions formed in the fin aside the gate. In order to form the various portions of the finFET according to replacement metal gate (RMG) approach, an elongated dummy gate is put in place where the metal gate conductor will eventually be placed perpendicularly across the fins. The dummy gate allows for processing such as anneals to be carried out without damaging the final gate conductor material. Spaces between the dummy gates and fins are filled with an interlayer dielectric. The dummy gates are typically made of polysilicon or amorphous silicon with a liner spacer such as titanium nitride. As part of the process, a gate cut opening is formed in the dummy gate, and is then filled with a gate cut fill. To form the finFETs, the dummy gate is removed, and replaced with a metal gate conductor that extends over adjacent fins. The gate cut fill creates a gate cut isolation that provides an electrical isolation between gates of adjacent finFETs to electrically isolate the finFETs.
As integrated circuit (IC) fabrication continues to scale to smaller technology nodes, e.g., 7 nanometers and beyond, spacing between structures continues to decrease. For example, ground rules and pattern variability lead to extremely tight spacing for gate cut openings during finFET formation. A particular challenge with forming the gate cut is creating the opening with the desired size. For example, the width for a gate cut opening is typically about 30 nanometers (nm), which allows sufficient space to remove any residue from the opening. However, that size is becoming too large for 7 nm technology node finFETs. That is, the gate cut fill size needs to be smaller than 30 nm to provide sufficient spacing, and to ensure metal gate conductor separation after metal conductor replacement in a 7 nm technology node. More specifically, in the 7 nm technology node, the amorphous silicon and liner spacer pinch off in a narrow gate cut, making it very difficult to remove the amorphous silicon residue at the bottom of the opening with the conventional reactive ion etch (RIE). In one approach, a high bias power RIE overetch is applied, but this etch creates bowed sidewalls in the gate cut opening, which can create shorts with the gate conductor ends. This approach can also reduce the space between the gate cut isolation and the active region to a level at which the high dielectric metal gate material cannot be formed over the active region next to the gate cut isolation, i.e., formation of a work function metal layer as part of the replacement metal gate process.